Low - Power Low - Jitter On - Chip Clock Generation
نویسندگان
چکیده
منابع مشابه
A Low-Power Multiplying DLL for Low-Jitter Multigigahertz Clock Generation in Highly Integrated Digital Chips
A multiplying delay-locked loop (MDLL) for highspeed on-chip clock generation that overcomes the drawbacks of phase-locked loops (PLLs) such as jitter accumulation, high sensitivity to supply, and substrate noise is described. The MDLL design removes such drawbacks while maintaining the advantages of a PLL for multirate frequency multiplication. This design also uses a supply regulator and filt...
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